| Presentation | 2009-09-24 A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages Masaki KINOSHITA, Yoichi TOMIOKA, Atsushi TAKAHASHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A BGA package realizes a lot of connections between a chip and a printed board. The quality of routing design obtained by manual is high, but it takes much time since it must take a lot of constraints into account. For example, vias must be arranged in appropriate positions so that they connect high-density routings between different layers while avoiding obstacles. Therefore, BGA package routing automation is required in industry. In this paper, we propose a detail via arrangement method that derives detailed routing patterns that satisfy the design rule of both layers from global routing patterns. Our proposed method is based on a dynamic programming. We show that our proposed method obtains an optimum detail via arrangement in almost linear time in terms of the number of rows of vias. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BGA package / package routing / detail via arrangement |
| Paper # | VLD2009-30 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/9/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages |
| Sub Title (in English) | |
| Keyword(1) | BGA package |
| Keyword(2) | package routing |
| Keyword(3) | detail via arrangement |
| 1st Author's Name | Masaki KINOSHITA |
| 1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
| 2nd Author's Name | Yoichi TOMIOKA |
| 2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| 3rd Author's Name | Atsushi TAKAHASHI |
| 3rd Author's Affiliation | Division of Electrical, Electronic and Information Engineering, Osaka University |
| Date | 2009-09-24 |
| Paper # | VLD2009-30 |
| Volume (vol) | vol.109 |
| Number (no) | 201 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |