| Presentation | 2009-09-18 An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters Shota ISHIHARA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an asynchronous FPGA that combines the 4-phase dual-rail encoding and the Level-Encoded Dual-Rail (LEDR) encoding. The 4-phase dual-rail encoding is employed to achieve small area for function units, while the LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters are also proposed in transistor-level optimization. The proposed architecture is designed using a 90nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput and the power consumption are respectively by 45% higher and by 36% lower with almost the same transisitor count. Compared to the LEDR-based FPGA, the transistor count is by 35% lower with almost the same power consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable VLSI / Field-programmable VLSI / LEDR (Level-Encoded Dual-Rail) encoding / 4-phase dual-rail encoding / Self-timed architecture |
| Paper # | RECONF2009-36 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/9/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable VLSI |
| Keyword(2) | Field-programmable VLSI |
| Keyword(3) | LEDR (Level-Encoded Dual-Rail) encoding |
| Keyword(4) | 4-phase dual-rail encoding |
| Keyword(5) | Self-timed architecture |
| 1st Author's Name | Shota ISHIHARA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Yoshiya KOMATSU |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Masanori HARIYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 4th Author's Name | Michitaka KAMEYAMA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2009-09-18 |
| Paper # | RECONF2009-36 |
| Volume (vol) | vol.109 |
| Number (no) | 198 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |