| Presentation | 2009-09-18 A Study of Scalable Prototyping System with Small-sized FPGAs Shimpei WATANABE, Shinya TAKAMAEDA, Ken KYOU, Takefumi MIYOSHI, Kenji KISE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In order to practically simulate many-core processor, the authors proposed ScalableCore which is a hardware simulator. ScalableCore consists of Simulation nodes named ScalableCore unit, which correspond to cores in the target processor, and common interfaces named ScalableCore Board, which connects simulation nodes. Since each Scalable board can connect four ScalableCore units around it, ScalableCore can achieve high scalability. It is proposed to implement ScalableCore onto a lot of small-sized FPGAs. The proposed method can reduce the complexity which is a major problem, by implementing each ScalableCore unit onto a small-sized FPGA. And the method can also provide sufficiently required I/O ports for local memory, because of implementation by using independent packages. In this paper, a primary version of the proposed implementation is shown and the simulating speed is estimated. By the result, it is shown that simulating speed of this implementation is 7x speeds over software simulator. It is not enough and much more effective implementation is required. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Many-core processor / evaluation environment / prototyping |
| Paper # | RECONF2009-31 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/9/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of Scalable Prototyping System with Small-sized FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Many-core processor |
| Keyword(3) | evaluation environment |
| Keyword(4) | prototyping |
| 1st Author's Name | Shimpei WATANABE |
| 1st Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology() |
| 2nd Author's Name | Shinya TAKAMAEDA |
| 2nd Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology |
| 3rd Author's Name | Ken KYOU |
| 3rd Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology |
| 4th Author's Name | Takefumi MIYOSHI |
| 4th Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology:JST |
| 5th Author's Name | Kenji KISE |
| 5th Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology |
| Date | 2009-09-18 |
| Paper # | RECONF2009-31 |
| Volume (vol) | vol.109 |
| Number (no) | 198 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |