Presentation 2009-09-18
Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE
Ken'ichi UMEDA, Yasuhiro NISHINAGA, Kazuya TANIGAWA, Tetsuo HIRONAKA,
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Abstract(in English) We have developed reconfigurable processor DS-HIE based on bit-serial operation. The merit of bit-serial operation is that it can implement more bit-serial operation units in a chip, compared with bit-parallel operation units. Therefore, many operation units enable high parallel processing on DS-HIE processor. But, parallel processing needs higher data transfer rate to utilize the parallel processing ability. To develop such a data transfer unit, we evaluated the requirements of data transfer, and then examine the structure of data transfer unit to satisfy the requirement.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Reconfigurable Processor / DS-HIE / Data Transfer Unit / Bit-serial Operation
Paper # RECONF2009-29
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Conference Information
Committee RECONF
Conference Date 2009/9/10(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE
Sub Title (in English)
Keyword(1) Reconfigurable Processor
Keyword(2) DS-HIE
Keyword(3) Data Transfer Unit
Keyword(4) Bit-serial Operation
1st Author's Name Ken'ichi UMEDA
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Yasuhiro NISHINAGA
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
3rd Author's Name Kazuya TANIGAWA
3rd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
4th Author's Name Tetsuo HIRONAKA
4th Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
Date 2009-09-18
Paper # RECONF2009-29
Volume (vol) vol.109
Number (no) 198
Page pp.pp.-
#Pages 6
Date of Issue