| Presentation | 2009-09-18 A Proposal for a Method to Generate an Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation Yasuhiro NISHINAGA, Ken'ichi UMEDA, Kazuya TANIGAWA, Tetsuo HIRONAKA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Our laboratory has developed a reconfigurable processor DS-HIE based on bit-serial operation. The DS-HIE processor achieves high performance by throughput, because bit-serial computation manner has a large latency. To achieve high performance by throughput with the DS-HIE processor, input timing at each operation unit of the DS-HIE is important. If there is a difference to the input to a operation unit, the DS-HIE cannot achieve high performance. So, to achieve high performance by throughput, it is necessary to generate the data-flow graph which mapped on the DS-HIE and adjusted timing to improve the problem. In this paper, we propose a method to generate an optimized dataflow graph by a compiler. The benchmark programs to evaluate the impact of the optimization were DCT and FIR. The result shows that it can achieve three times higher performance with the optimization. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable processor / DS-HIE / optimization / data-flow graph / bit-serial operation |
| Paper # | RECONF2009-28 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/9/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Proposal for a Method to Generate an Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable processor |
| Keyword(2) | DS-HIE |
| Keyword(3) | optimization |
| Keyword(4) | data-flow graph |
| Keyword(5) | bit-serial operation |
| 1st Author's Name | Yasuhiro NISHINAGA |
| 1st Author's Affiliation | Graduate school of information Sciences, Hiroshima City University() |
| 2nd Author's Name | Ken'ichi UMEDA |
| 2nd Author's Affiliation | Graduate school of information Sciences, Hiroshima City University |
| 3rd Author's Name | Kazuya TANIGAWA |
| 3rd Author's Affiliation | Graduate school of information Sciences, Hiroshima City University |
| 4th Author's Name | Tetsuo HIRONAKA |
| 4th Author's Affiliation | Graduate school of information Sciences, Hiroshima City University |
| Date | 2009-09-18 |
| Paper # | RECONF2009-28 |
| Volume (vol) | vol.109 |
| Number (no) | 198 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |