| Presentation | 2009-09-17 Leakage Power Reduction of a Dynamically Reconfigurable Processor with Deal Vth cells Hideharu AMANO, Keiichiro HIRAI, Toru SANO, Masaru KATO, Yoshiki SAITO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | One of benefit of coarse-grained dynamically reconfigurable processor arrays (DRPAs) is its low dynamic power consumption by operating a number of processing element (PE) in parallel with low frequency. However, in the future advanced process, the leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power of DRPA without severe performance degradation, eight design policies (Mult, Sw, MultSw, MapHalf, 1Low, RandHalf, Sw+Half and SW+Mult) with Dual-Vt cells are proposed and evaluated based on a prototype DRPA called MuCCRA-3T. Evaluation results show that Sw in which Low-Vt cells are only used in switching elements of the array achieved the best power-delay product. If performance of Sw is not enough, Sw+Half in which Low-Vt cells are used in a lower half PEs and all switching elements improve 24% of the leakage power with 5%-14% of extra delay time of the design with all Low-Vt cells. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable Processor / Low Power Design / Dual-Vth |
| Paper # | RECONF2009-26 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/9/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Leakage Power Reduction of a Dynamically Reconfigurable Processor with Deal Vth cells |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor |
| Keyword(2) | Low Power Design |
| Keyword(3) | Dual-Vth |
| 1st Author's Name | Hideharu AMANO |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Keiichiro HIRAI |
| 2nd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 3rd Author's Name | Toru SANO |
| 3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 4th Author's Name | Masaru KATO |
| 4th Author's Affiliation | Faculty of Science and Technology, Keio University |
| 5th Author's Name | Yoshiki SAITO |
| 5th Author's Affiliation | Faculty of Science and Technology, Keio University |
| Date | 2009-09-17 |
| Paper # | RECONF2009-26 |
| Volume (vol) | vol.109 |
| Number (no) | 198 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |