| Presentation | 2009-06-24 Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier Joung-eob Lee, Kwon-Chil Kang, Jung Han Lee, Byung-Gook Park, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Single electron transistors (SETs) are lively searched as a promising device beyond the scaling limits of CMOS (Complementary Metal Oxide Semiconductor) devices. Among the various SETs that have been reported, the vertical island (VI) SET uses a fabrication process which is compatible with CMOS and has the advantage of effectively controlling the device characteristics with its device parameters. Device simulation is performed to optimize the device parameters, and a structure that may operate the presentation of various function in the circuit and device. VI-SET device will be using the multi function circuit and qubit through the double quantum dot in the devices. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Single Electron Transistor / CMOS / Quantum Dot |
| Paper # | ED2009-65,SDM2009-60 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2009/6/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier |
| Sub Title (in English) | |
| Keyword(1) | Single Electron Transistor |
| Keyword(2) | CMOS |
| Keyword(3) | Quantum Dot |
| 1st Author's Name | Joung-eob Lee |
| 1st Author's Affiliation | Inter-University Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University() |
| 2nd Author's Name | Kwon-Chil Kang |
| 2nd Author's Affiliation | Inter-University Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University |
| 3rd Author's Name | Jung Han Lee |
| 3rd Author's Affiliation | Inter-University Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University |
| 4th Author's Name | Byung-Gook Park |
| 4th Author's Affiliation | Inter-University Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University |
| Date | 2009-06-24 |
| Paper # | ED2009-65,SDM2009-60 |
| Volume (vol) | vol.109 |
| Number (no) | 98 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |