| Presentation | 2009-06-24 Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits F. Iga, M. Kamiyanagi, S. Ikeda, K. Miura, J. Hayakawa, H. Hasegawa, T. Hanyu, H. Ohno, T. Endoh, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/1-poly Gate 0.14μm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60x180nm^2 achieves a large change in resistance of 3.52kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320μA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | magnetic tunnel junction (MTJ) / spin-transfer torque RAM (STT-RAM) / memory-in-logic / MgO barrier / spintronics / tunnel magnetoresistance (TMR) / magnetoresistive RAM (MRAM) / current-induced magnetization switching |
| Paper # | ED2009-53,SDM2009-48 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2009/6/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits |
| Sub Title (in English) | |
| Keyword(1) | magnetic tunnel junction (MTJ) |
| Keyword(2) | spin-transfer torque RAM (STT-RAM) |
| Keyword(3) | memory-in-logic |
| Keyword(4) | MgO barrier |
| Keyword(5) | spintronics |
| Keyword(6) | tunnel magnetoresistance (TMR) |
| Keyword(7) | magnetoresistive RAM (MRAM) |
| Keyword(8) | current-induced magnetization switching |
| 1st Author's Name | F. Iga |
| 1st Author's Affiliation | Center for Interdisciplinary Research, Tohoku University() |
| 2nd Author's Name | M. Kamiyanagi |
| 2nd Author's Affiliation | Center for Interdisciplinary Research, Tohoku University |
| 3rd Author's Name | S. Ikeda |
| 3rd Author's Affiliation | Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University |
| 4th Author's Name | K. Miura |
| 4th Author's Affiliation | Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University:Hitachi Advanced Research Laboratory |
| 5th Author's Name | J. Hayakawa |
| 5th Author's Affiliation | Hitachi Advanced Research Laboratory |
| 6th Author's Name | H. Hasegawa |
| 6th Author's Affiliation | Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University |
| 7th Author's Name | T. Hanyu |
| 7th Author's Affiliation | Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University |
| 8th Author's Name | H. Ohno |
| 8th Author's Affiliation | Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University |
| 9th Author's Name | T. Endoh |
| 9th Author's Affiliation | Center for Interdisciplinary Research, Tohoku University |
| Date | 2009-06-24 |
| Paper # | ED2009-53,SDM2009-48 |
| Volume (vol) | vol.109 |
| Number (no) | 98 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |