Presentation 2009-08-04
BER Performance Comparison between Sliding Window Chip Equalizer and Overlap FDE on DS-CDMA
Tatsunori OBARA, Kazuki TAKEDA, Fumiyuki ADACHI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) In signal transmission using direct sequence code division multiple access (DS-CDMA), frequency-domain equalization (FDE) based on minimum mean square error (MMSE) criterion can achieve much better performance than the well-known rake combining. The conventional FDE requires the insertion of guard interval (GI) to avoid the inter-block interference (IBI). However, the GI insertion reduces the throughput. Recently, overlap FDE that requires no GI insertion was proposed. Another equalization technique is a time-domain sliding window chip equalizer (SWCE) based on MMSE criterion. In this paper, we evaluate and compare the bit error rate (BER) performance of multicode DS-CDMA using SWCE and overlap FDE by computer simulation.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Sliding Window Chip Equalizer (SWCE) / overlap FDE / DS-CDMA
Paper # RCS2009-94
Date of Issue

Conference Information
Committee RCS
Conference Date 2009/7/27(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Radio Communication Systems (RCS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) BER Performance Comparison between Sliding Window Chip Equalizer and Overlap FDE on DS-CDMA
Sub Title (in English)
Keyword(1) Sliding Window Chip Equalizer (SWCE)
Keyword(2) overlap FDE
Keyword(3) DS-CDMA
1st Author's Name Tatsunori OBARA
1st Author's Affiliation Dept. of Electrical and Communication Engineering, Graduate School of Engineering, Tohoku University()
2nd Author's Name Kazuki TAKEDA
2nd Author's Affiliation Dept. of Electrical and Communication Engineering, Graduate School of Engineering, Tohoku University
3rd Author's Name Fumiyuki ADACHI
3rd Author's Affiliation Dept. of Electrical and Communication Engineering, Graduate School of Engineering, Tohoku University
Date 2009-08-04
Paper # RCS2009-94
Volume (vol) vol.109
Number (no) 164
Page pp.pp.-
#Pages 6
Date of Issue