Presentation 2009/7/28
Evaluation of Communication Performance on ClearSpeed's SIMD Processor
Yuri NISHIKAWA, Michihiro KOIBUCHI, Masato YOSHIMI, Akihiro SHITARA, Kenichi MIURA, Hideharu AMANO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) ClearSpeed's CSX600 that consists of 96 Processing Elements (PEs) employs a one-dimensional array topology for a simple SIMD processing. To clearly show its performance factors, this paper measures and analyzes NoCs of CSX600 called Swazzle and ClearConnect. Evaluation and analysis results show that the sending and receiving overheads are the major limitation factors of their effective bandwidth. We found that (1) number of validated PEs, (2) size of transferred data, and (3) data alignment of a shared memory are three main points to make the best use of bandwidth. In addition, we estimated the best- and worst-case latencies of data transfers in parallel applications.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SIMD processor / Many-core / Network-on-a-Chip (NoC) / communication performance
Paper # CPSY2009-25
Date of Issue

Conference Information
Committee CPSY
Conference Date 2009/7/28(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of Communication Performance on ClearSpeed's SIMD Processor
Sub Title (in English)
Keyword(1) SIMD processor
Keyword(2) Many-core
Keyword(3) Network-on-a-Chip (NoC)
Keyword(4) communication performance
1st Author's Name Yuri NISHIKAWA
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Michihiro KOIBUCHI
2nd Author's Affiliation National Institute of Informatics
3rd Author's Name Masato YOSHIMI
3rd Author's Affiliation Faculty of Science and Engineering, Doshisha University
4th Author's Name Akihiro SHITARA
4th Author's Affiliation Graduate School of Science and Technology, Keio University
5th Author's Name Kenichi MIURA
5th Author's Affiliation National Institute of Informatics
6th Author's Name Hideharu AMANO
6th Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2009/7/28
Paper # CPSY2009-25
Volume (vol) vol.109
Number (no) 168
Page pp.pp.-
#Pages 6
Date of Issue