| Presentation | 2009/7/28 Error detection and collectionon mechanism on Network-on-Chip Yu KOJIMA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We evaluate and propose a low-power method based on error-tolerant techniques in order to reduce the supply voltage while maintaining the error rate on Network-on-Chip (NoC). This method aims to optimize the power consumptoin of NoC by dynamically selecting the best error-tolerant technique. Evaluation results show that the error detection/correction techniques minimize the number of retransmitted packets due to soft errors, and this reduces 40% of the energy for sending a flit. In addition, applying a high-reliable error detection/correction technique to control information of a flit is efficient only when an error rate is high. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | CPSY2009-24 |
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| Committee | CPSY |
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| Conference Date | 2009/7/28(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Error detection and collectionon mechanism on Network-on-Chip |
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| 1st Author's Name | Yu KOJIMA |
| 1st Author's Affiliation | Graduate School of Science and Technology, Keio University() |
| 2nd Author's Name | Hiroki MATSUTANI |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
| 3rd Author's Name | Michihiro KOIBUCHI |
| 3rd Author's Affiliation | National Institution of Infomatics |
| 4th Author's Name | Hideharu AMANO |
| 4th Author's Affiliation | Graduate School of Science and Technology, Keio University |
| Date | 2009/7/28 |
| Paper # | CPSY2009-24 |
| Volume (vol) | vol.109 |
| Number (no) | 168 |
| Page | pp.pp.- |
| #Pages | 6 |
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