Presentation 2009/7/28
Experimental evaluation of a cloking scheme with relaxed timing constraints
Takanobu KITA, Shou TARUI, Ryota SHIOYA, Masahiro GOSHIMA, Shuichi SAKAI,
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Abstract(in English) The feature size of LSI is getting smaller year by year, increasing random variation between the elements. These days, the problem of the variation imposes too severe timing constrains to design circuit with enough timing margin. To overcome this problem, this paper proposes a clocking scheme with relaxed timing constrains. Our method separates logic paths into two kinds of paths, short path and critical path. The circuits will be allowed up to 1.5 clock cycle delay per stage, while existing method, two phase latch allows 1 clock cycle delay per stage. Timing margin produced by proposed method enables lower energy consumption and higher clock frequency.
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Keyword(in English) timing constraints / cloking scheme / two-phase latch / time borrowing
Paper # CPSY2009-20
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Committee CPSY
Conference Date 2009/7/28(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Experimental evaluation of a cloking scheme with relaxed timing constraints
Sub Title (in English)
Keyword(1) timing constraints
Keyword(2) cloking scheme
Keyword(3) two-phase latch
Keyword(4) time borrowing
1st Author's Name Takanobu KITA
1st Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo()
2nd Author's Name Shou TARUI
2nd Author's Affiliation HITACHI Ltd.
3rd Author's Name Ryota SHIOYA
3rd Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo
4th Author's Name Masahiro GOSHIMA
4th Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo
5th Author's Name Shuichi SAKAI
5th Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo
Date 2009/7/28
Paper # CPSY2009-20
Volume (vol) vol.109
Number (no) 168
Page pp.pp.-
#Pages 6
Date of Issue