| Presentation | 2009/7/29 A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling Naoya ONIZAWA, Atsushi MATSUMOTO, Takahiro HANYU, Tomohiro YONEDA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling under the power-supply/voltage and process variations. Since distance between two multi-level codewords which includes data and control information are minimized, the maximum logical value can be reduced with a correct asynchronous data transfer. Moreover, a logical value used for detection of an asynchronous signal is assigned a large amount of current in comparison that which is not used for detection, which increases a voltage margin of a unit logical value. In the circuit implementation, a compensation circuit with a characteristic which is inversely changed to that of an operation circuit under the power/voltage variations is closely placed on the operation circuit, thus the characteristic of the operation circuit becomes almost stable. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous circuits / multiple-valued current-mode circuit / dual-rail encoding / Network-on-Chip |
| Paper # | DC2009-18 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2009/7/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuits |
| Keyword(2) | multiple-valued current-mode circuit |
| Keyword(3) | dual-rail encoding |
| Keyword(4) | Network-on-Chip |
| 1st Author's Name | Naoya ONIZAWA |
| 1st Author's Affiliation | Research Institute of Electrical Communication, Tohoku University() |
| 2nd Author's Name | Atsushi MATSUMOTO |
| 2nd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University |
| 3rd Author's Name | Takahiro HANYU |
| 3rd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University |
| 4th Author's Name | Tomohiro YONEDA |
| 4th Author's Affiliation | Information Systems Architecture Science Research Division, National Institute of Informatics |
| Date | 2009/7/29 |
| Paper # | DC2009-18 |
| Volume (vol) | vol.109 |
| Number (no) | 169 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |