Presentation 2009-06-19
An Area Reduction Technique of Self-testing FFs for Small-delay Defects Detection
Koichiro NOGUCHI, Koichi NOSE, Toshinobu ONO, Masayuki MIZUNO,
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Abstract(in English) As continuous process scaling produces large-scale chips, small-delay defects become one of the major chip-reliability limiters. Small-delay defect detection techniques for LSI screening have been developed, which can successfully detect outlier chips among normally-distributed chips using a self-testing scan-FF. In this paper, Area reduction technique is proposed. As a result, we realized 10% chip area reduction by sharing a part of functions of self-testing FF among the some scan-FF.
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Keyword(in English) Delay defect / Test / Screening / Scan-FF
Paper # DC2009-16
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Conference Date 2009/6/12(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Area Reduction Technique of Self-testing FFs for Small-delay Defects Detection
Sub Title (in English)
Keyword(1) Delay defect
Keyword(2) Test
Keyword(3) Screening
Keyword(4) Scan-FF
1st Author's Name Koichiro NOGUCHI
1st Author's Affiliation Device Platforms Research Laboratories, NEC Corporation()
2nd Author's Name Koichi NOSE
2nd Author's Affiliation Device Platforms Research Laboratories, NEC Corporation
3rd Author's Name Toshinobu ONO
3rd Author's Affiliation Design Engineering Development Division, NEC Electronics Corporation
4th Author's Name Masayuki MIZUNO
4th Author's Affiliation Device Platforms Research Laboratories, NEC Corporation
Date 2009-06-19
Paper # DC2009-16
Volume (vol) vol.109
Number (no) 95
Page pp.pp.-
#Pages 4
Date of Issue