| Presentation | 2009-06-19 High-level Design for Test Tools & Industrial Design Flows Chouki AKTOUF, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Design for Testability at Register Transfer Level has been widely explored by academia. Commercial tools start to be considered in industrial design flows. This talk presents the current status of using RTL DFT solutions in industry with a tentative forecast of the future. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RTL descriptions / Verilog / VHDL / Testability analysis / DFT methodologies & techniques |
| Paper # | DC2009-14 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2009/6/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-level Design for Test Tools & Industrial Design Flows |
| Sub Title (in English) | |
| Keyword(1) | RTL descriptions |
| Keyword(2) | Verilog |
| Keyword(3) | VHDL |
| Keyword(4) | Testability analysis |
| Keyword(5) | DFT methodologies & techniques |
| 1st Author's Name | Chouki AKTOUF |
| 1st Author's Affiliation | DeFacTo Technologies() |
| Date | 2009-06-19 |
| Paper # | DC2009-14 |
| Volume (vol) | vol.109 |
| Number (no) | 95 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |