Presentation	2009-06-19 Design method of easily testable parallel prefix adders Hidetoshi SUZUKI, Nafumi TAKAGI,
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Abstract(in English)	We propose a design method of easily testable parallel prefix adders. In a parallel prefix adder, the prefix computation, i.e., computation of carry generation and propagation condition from the least significant position to each bit position is performed in parallel. There are several configurations of the prefix computation circuit, and hence, we can design a parallel prefix adder that fits a given requirement on the computation time, area etc. We can design an n-bit adder which can be tested with 24n-2 patterns under the cell fault model, by introducing an additional input line and modifying the functions of the cells of four kinds.
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Keyword(in English)	Design for testability / parallel prefix adder
Paper #	DC2009-10
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Committee	DC
Conference Date	2009/6/12(1days)
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Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Design method of easily testable parallel prefix adders
Sub Title (in English)
Keyword(1)	Design for testability
Keyword(2)	parallel prefix adder
1st Author's Name	Hidetoshi SUZUKI
1st Author's Affiliation	Department of Information Engineering, Nagoya University()
2nd Author's Name	Nafumi TAKAGI
2nd Author's Affiliation	Department of Information Engineering, Nagoya University
Date	2009-06-19
Paper #	DC2009-10
Volume (vol)	vol.109
Number (no)	95
Page	pp.pp.-
#Pages	6
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