| Presentation | 2009-03-04 FPGA Implementation of Trellis Shaping to Control Peak Power for PSK Signals and its Performance Evaluation Hiroyuki KITAGAWA, Makoto TANAHASHI, Hideki OCHIAI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Single-carrier (SC) transmission is considered as a promising candidate for the uplink of the next generation mobile systems due to its relatively low peak-to-average power ratio (PAR) compared to multi-carrier modulation such as orthogonal frequency division multiplexing (OFDM). In SC systems, bandwidth efficiency can be effectively enhanced by the use of waveform shaping filter with a low roll-off factor. However, as a price, the pulse-shaped signals incur non-negligible increase of PAR, even in the case of phase shift keying (PSK) modulations. To balance both the low PAR and the high bandwidth efficiency, the authors have proposed a PAR reduction technique for SC-PSK systems based on trellis shaping. In order to investigate the feasibility of the proposed trellis shaping system, we have implemented a transmitter by using Field Programmable Gate Array (FPGA). In this paper, we evaluate its effectiveness through testbed experiments with an RF power amplifier (PA). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Trellis Shaping / Single-Carrier / PSK / Peak Power / FPGA |
| Paper # | RCS2008-214 |
| Date of Issue |
| Conference Information | |
| Committee | RCS |
|---|---|
| Conference Date | 2009/2/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Radio Communication Systems (RCS) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Implementation of Trellis Shaping to Control Peak Power for PSK Signals and its Performance Evaluation |
| Sub Title (in English) | |
| Keyword(1) | Trellis Shaping |
| Keyword(2) | Single-Carrier |
| Keyword(3) | PSK |
| Keyword(4) | Peak Power |
| Keyword(5) | FPGA |
| 1st Author's Name | Hiroyuki KITAGAWA |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Makoto TANAHASHI |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 3rd Author's Name | Hideki OCHIAI |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| Date | 2009-03-04 |
| Paper # | RCS2008-214 |
| Volume (vol) | vol.108 |
| Number (no) | 445 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |