Presentation	2009-03-12 Chip evaluation and implementation of DES encryption using via-programmable-device VPEX Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Syouta Yamada, Masaya Yoshikawa, Takeshi Fujino,
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Abstract(in English)	We have been studied the via-programmable-device VPEX (V___ia P___rogrammable logic using ___clusive or array) whose logic element consists of the combination of complex-gate-type EXOR gate and Inverter. 12 kinds of logic functions including all two-input and one-output functions can be programmed by changing via-1 layout. Various kinds of combination logics are configured by changing via-3 layout which controls the connection between LEs. Register (DFF: D Flip Flops) can be realized by using some LEs, so sequential-logic is also programmed in the LE array. In this study, we have designed the test chip which has small-scale circuits using VPEX architecture, and check the operation of each logic functions. We improved the elements of LE and realized the decrease of circuit area. As an example of circuit implementation, we applied VPEX architecture to DES encryption circuit, and evaluated the chip area of VPEX compared to that of Standard Cells.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Via-programmable-logic / EB direct writing / Exclusive-OR / DES encryption
Paper #	VLD2008-139
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Committee	VLD
Conference Date	2009/3/4(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Chip evaluation and implementation of DES encryption using via-programmable-device VPEX
Sub Title (in English)
Keyword(1)	Via-programmable-logic
Keyword(2)	EB direct writing
Keyword(3)	Exclusive-OR
Keyword(4)	DES encryption
1st Author's Name	Masahide Kawarasaki
1st Author's Affiliation	Graduate school of Science and Engineering, Ritsumeikan University()
2nd Author's Name	Tomohiro Nishimoto
2nd Author's Affiliation	Graduate school of Science and Engineering, Ritsumeikan University
3rd Author's Name	Yuuichi Kokushou
3rd Author's Affiliation	Graduate school of Science and Engineering, Ritsumeikan University
4th Author's Name	Kazuma Kitamura
4th Author's Affiliation	Graduate school of Science and Engineering, Ritsumeikan University
5th Author's Name	Syouta Yamada
5th Author's Affiliation	Graduate school of Science and Engineering, Ritsumeikan University
6th Author's Name	Masaya Yoshikawa
6th Author's Affiliation	Faculty of Science and Engineering, Meijou University
7th Author's Name	Takeshi Fujino
7th Author's Affiliation	Graduate school of Science and Engineering, Ritsumeikan University
Date	2009-03-12
Paper #	VLD2008-139
Volume (vol)	vol.108
Number (no)	478
Page	pp.pp.-
#Pages	6
Date of Issue