| Presentation | 2009-03-11 A Maximization Method of Parallel Wire Lengths in Routing Area with Obstacles Suguru SUEHIRO, Yukihide KOHIRA, Atsushi TAKAHASHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Due to the speeding up of VLSI systems, the PCB routing design is requested to take signal delay and signal integrity into account. Our goal is to develop a routing method for PCB in which signal delay and signal integrity are taken into account. In this paper, in order to evaluate the routing area which is assigned to differential pair nets, we propose a routing method for routing area with obstacles that generates a longer completely parallel dual path. In experiment, the effectiveness of our proposed method is confirmed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | specified length routing / parallel wire / maximum wire length / PCB / amount of delay |
| Paper # | VLD2008-136 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/3/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Maximization Method of Parallel Wire Lengths in Routing Area with Obstacles |
| Sub Title (in English) | |
| Keyword(1) | specified length routing |
| Keyword(2) | parallel wire |
| Keyword(3) | maximum wire length |
| Keyword(4) | PCB |
| Keyword(5) | amount of delay |
| 1st Author's Name | Suguru SUEHIRO |
| 1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
| 2nd Author's Name | Yukihide KOHIRA |
| 2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| 3rd Author's Name | Atsushi TAKAHASHI |
| 3rd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| Date | 2009-03-11 |
| Paper # | VLD2008-136 |
| Volume (vol) | vol.108 |
| Number (no) | 478 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |