| Presentation | 2009-03-10 Hardware Implementations of the Cryptographic Hash Function Family AURORA Toru AKISHITA, Tadaoki YAMAMOTO, Hiroyuki ABE, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents optimization techniques and evaluation results in hardware implementations of the hash function family AURORA. Each component in F-functions of AURORA can be implemented efficiently in hardware, and its design enables a variety of implementations, from high-speed to area-restricted implementations. In our evaluations using a 0.13μm CMOS ASIC library, AURORA-256 achieves the highest throughput of 10.4Gbps with area of 35.0Kgate in a speed-optimized implementation, and the smallest area of 8.9Kgate with throughput of 1.1Gbps in an area-optimized implementation. AURORA-512 achieves the highest throughput of 9.1Gbps in a speed-optimized implementation, and the smallest area of 12.1Kgate in an area-optimized implementation. These figures are so advantageous to the best known results of hardware performance of SHA-2 that AURORA is a highly efficient hash function family in hardware implementation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hash function / AURORA / hardware implementation |
| Paper # | IT2008-88,ISEC2008-146,WBS2008-101 |
| Date of Issue |
| Conference Information | |
| Committee | WBS |
|---|---|
| Conference Date | 2009/3/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Wideband System(WBS) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Implementations of the Cryptographic Hash Function Family AURORA |
| Sub Title (in English) | |
| Keyword(1) | hash function |
| Keyword(2) | AURORA |
| Keyword(3) | hardware implementation |
| 1st Author's Name | Toru AKISHITA |
| 1st Author's Affiliation | Sony Corporation() |
| 2nd Author's Name | Tadaoki YAMAMOTO |
| 2nd Author's Affiliation | Sony LSI Design Inc. |
| 3rd Author's Name | Hiroyuki ABE |
| 3rd Author's Affiliation | Sony LSI Design Inc. |
| Date | 2009-03-10 |
| Paper # | IT2008-88,ISEC2008-146,WBS2008-101 |
| Volume (vol) | vol.108 |
| Number (no) | 474 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |