| Presentation | 2009-03-06 A implementation of RSA encryption using Interleaved Modular Multiplication for MX Core Wataru KUROKI, Masahiro IIDA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | MX Core is a massively parallel SIMD (Single Instruction Multiple Data) type processor which have fine-grained computing units (PE: Prpcessing Element). The main target of operation in MX Core is multimedia processing. Therefore the MX core does not assume the implementation of the application that handle the multiprecision integer with several thousands bits. In this paper, we focus on the RSA encryption which is a kind of public-key crypto system with multiprecision integer arithmetic operation. Then we report the implementation method of the RSA encryption, which use the interleaved modular multiplication, and describe the evaluation result. From the simulation result, the throughput of 2,048-bit RSA encryption reaches to 1,550kbps on the MX Core that the processing frequency is 200MHz. As compared with the conventional implementation, the number of cycles is reduced by 31.7% and the throughput has improved 2.92 times. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MX Core / RSA / SIMD |
| Paper # | CPSY2008-102,DC2008-93 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2009/2/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A implementation of RSA encryption using Interleaved Modular Multiplication for MX Core |
| Sub Title (in English) | |
| Keyword(1) | MX Core |
| Keyword(2) | RSA |
| Keyword(3) | SIMD |
| 1st Author's Name | Wataru KUROKI |
| 1st Author's Affiliation | Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University() |
| 2nd Author's Name | Masahiro IIDA |
| 2nd Author's Affiliation | Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University |
| 3rd Author's Name | Toshinori SUEYOSHI |
| 3rd Author's Affiliation | Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University |
| Date | 2009-03-06 |
| Paper # | CPSY2008-102,DC2008-93 |
| Volume (vol) | vol.108 |
| Number (no) | 464 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |