Presentation 2009-03-06
Design and Implementation of the Thread Scheduling Scheme for Responsive Multithreaded Processor
Hiroyuki UMEO, Kazutoshi SUITO, Akira TAKEDA, Shinpei KATO, Nobuyuki YAMASAKI,
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Abstract(in English) Responsive Multithreaded Processor for real-time processing can execute eight threads simultaneously in priority order without context switching. When over nine threads are executed, context switching is required. A real-time scheduler should be called periodically and release times of all tasks are checked. This paper proposes thread scheduling scheme for RMT Processor. RMT PU, which is processing core of RMT processor, holds the periods of all threads and starts threads by hardware without periodic calls of the scheduler. In addition, threads in context cache are compared with threads in execution, and context switching will be realized by hardware. Our thread scheduling scheme reduces scheduling overheads so that traditional software scheduling can be unnecessary.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) RMT Processor / Scheduling Overhead / Thread Scheduling
Paper # CPSY2008-97,DC2008-88
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Committee DC
Conference Date 2009/2/26(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Implementation of the Thread Scheduling Scheme for Responsive Multithreaded Processor
Sub Title (in English)
Keyword(1) RMT Processor
Keyword(2) Scheduling Overhead
Keyword(3) Thread Scheduling
1st Author's Name Hiroyuki UMEO
1st Author's Affiliation Department of Information and Computer Science, Faculty of Science and Technology, Keio University()
2nd Author's Name Kazutoshi SUITO
2nd Author's Affiliation Department of Computer Science, Graduate School of Science and Technology, Keio University
3rd Author's Name Akira TAKEDA
3rd Author's Affiliation Department of Computer Science, Graduate School of Science and Technology, Keio University
4th Author's Name Shinpei KATO
4th Author's Affiliation Department of Computer Science, Graduate School of Science and Technology, Keio University
5th Author's Name Nobuyuki YAMASAKI
5th Author's Affiliation Department of Computer Science, Graduate School of Science and Technology, Keio University
Date 2009-03-06
Paper # CPSY2008-97,DC2008-88
Volume (vol) vol.108
Number (no) 464
Page pp.pp.-
#Pages 6
Date of Issue