Presentation 2009-03-05
Debugging Support for Synchronization of Parallel Execution in System Level Designs
Hiroki HARADA, Tasuku NISHIHARA, Takeshi MATSUMOTO, Masahiro FUJITA,
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Abstract(in English) There are many high-level designs contain parallel execution, synchronization, or communication, and they are often error-prone. In this work, we propose a debugging support method for designs with improper synchronization. We derive a safe condition by static analysis in which synchronization works properly under the target design. The experiment with an elevator controller containing parallel executions shows that we can easily check whether synchronization works as the designer intended or not, by using the derived condition.
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Keyword(in English) System level design / Synchronization verification / Symbolic simulation
Paper # CPSY2008-94,DC2008-85
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Committee DC
Conference Date 2009/2/26(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Debugging Support for Synchronization of Parallel Execution in System Level Designs
Sub Title (in English)
Keyword(1) System level design
Keyword(2) Synchronization verification
Keyword(3) Symbolic simulation
1st Author's Name Hiroki HARADA
1st Author's Affiliation Dept. of Electronics Engineering, Faculty of Engineering, The University of Tokyo()
2nd Author's Name Tasuku NISHIHARA
2nd Author's Affiliation Dept. of Electronics Engineering, Graduate School of Engineering, The University of Tokyo
3rd Author's Name Takeshi MATSUMOTO
3rd Author's Affiliation VLSI Design and Education Center, The University of Tokyo
4th Author's Name Masahiro FUJITA
4th Author's Affiliation VLSI Design and Education Center, The University of Tokyo:Core Research for Evolutional Science and Technology, Japan Science and Technology Agency
Date 2009-03-05
Paper # CPSY2008-94,DC2008-85
Volume (vol) vol.108
Number (no) 464
Page pp.pp.-
#Pages 6
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