Presentation 2009-03-05
A Dynamic Management Technique of a Non-uniform Selective Way Cache for Reducing the Energy Consumption of Embedded Processors
Yuriko ISHITOBI, Tohru ISHIHARA, Hiroto YASUURA,
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Abstract(in English) This paper proposes a dynamic management technique of Non-uniform Selective Way Cache (NSWC) for reducing the total energy consumption of a CPU core, cache memories, and off-chip memories. NSWC has a way uses low supply (Vdd) and low threshould (Vth). In our approach, we decide insert points of instructions to change available ways in the Non-uniform Selective Way Cache. Experiments using parameters of a commercial embedded processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 7%-20% compared to the result of a processor with a same size set associative cache memory.
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Keyword(in English) embedded processor / energy reduction / cache memory
Paper # CPSY2008-90,DC2008-81
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Committee DC
Conference Date 2009/2/26(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Dynamic Management Technique of a Non-uniform Selective Way Cache for Reducing the Energy Consumption of Embedded Processors
Sub Title (in English)
Keyword(1) embedded processor
Keyword(2) energy reduction
Keyword(3) cache memory
1st Author's Name Yuriko ISHITOBI
1st Author's Affiliation Graduate School of Inf. Sci. & E.E., Kyushu University()
2nd Author's Name Tohru ISHIHARA
2nd Author's Affiliation System LSI Research Center, Kyushu University
3rd Author's Name Hiroto YASUURA
3rd Author's Affiliation Kyushu University
Date 2009-03-05
Paper # CPSY2008-90,DC2008-81
Volume (vol) vol.108
Number (no) 464
Page pp.pp.-
#Pages 6
Date of Issue