Presentation 2009-04-23
Ferroelectric-Gate Thin-Film-Transistor Memory Using Epitaxially Grown Composite-Oxide-Film
Yukihiro KANEKO, Hiroyuki TANAKA, Yoshihisa KATO, Yasuhiro SHIMADA,
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Abstract(in English) We have developed a ferroelectric-gate thin-film transistor (FeTFT) composed of heteroepitaxially stacked oxide materials. A bottom gate electrode of SrRuO_3 (SRO), a ferroelectric film of Pb(Zr,Ti)O_3 (PZT) and a semiconductor film of ZnO are grown on a SrTiO_3 (STO) substrate. Structural characterization shows a heteroepitaxy of the fabricated ZnO/PZT/SRO/STO structure with good crystalline quality and the absence of an interface reaction layer. When the polarization direction of the PZT film is downward, all the electrons across the ZnO film are depleted. When the polarization direction is upward, on the other hand, quasi-two-dimensional electron gas is accumulated at the ZnO/PZT interface. Drain and source electrodes of Pt/Ti are formed on the ZnO film and in-plane conduction at the ZnO/PZT interface is probed. When gate voltages applied to the bottom electrode are swept between -10 and 10V, the on/off ratio of drain currents is higher than 10^5. Such a high on/off ratio is preserved even after 10^5s. In addition, the FeTFT can write and read multi level datum.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) ferroelectric / ferroelectric-gate field-effect-transistor / ferroelectric memory / ZnO / SrTiO_3 / SrRuO_3 / Pb(Zr,Ti)O_3 / oxide semiconductor
Paper # ED2009-5
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Committee ED
Conference Date 2009/4/16(1days)
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Registration To Electron Devices (ED)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Ferroelectric-Gate Thin-Film-Transistor Memory Using Epitaxially Grown Composite-Oxide-Film
Sub Title (in English)
Keyword(1) ferroelectric
Keyword(2) ferroelectric-gate field-effect-transistor
Keyword(3) ferroelectric memory
Keyword(4) ZnO
Keyword(5) SrTiO_3
Keyword(6) SrRuO_3
Keyword(7) Pb(Zr,Ti)O_3
Keyword(8) oxide semiconductor
1st Author's Name Yukihiro KANEKO
1st Author's Affiliation Semiconductor Device Research Center, Semiconductor Company, Panasonic Corporation()
2nd Author's Name Hiroyuki TANAKA
2nd Author's Affiliation Semiconductor Device Research Center, Semiconductor Company, Panasonic Corporation
3rd Author's Name Yoshihisa KATO
3rd Author's Affiliation Semiconductor Device Research Center, Semiconductor Company, Panasonic Corporation
4th Author's Name Yasuhiro SHIMADA
4th Author's Affiliation Semiconductor Device Research Center, Semiconductor Company, Panasonic Corporation
Date 2009-04-23
Paper # ED2009-5
Volume (vol) vol.109
Number (no) 16
Page pp.pp.-
#Pages 6
Date of Issue