Presentation 2009-05-15
Acceleration of UPACS subroutines with FPGAs
Takaaki YOKOYAMA, Hirokazu MORISHITA, Yasunori OSANA, Naoyuki FUJITA, Hideharu AMANO,
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Abstract(in English) A cost effective reconfigurable processing engine using multiple FPGAs for accelerating UPACS, a CFD package produced by JAXA has been developed. Two kernels; error modification routine and time integral routine; have been implemented in our past research. Here, we implemented a pipelined structure of the third routine; cell face variables routine on Virtex-5 FPGAs. 209 times performance of a PC using Intel Core 2Duo (2.66GHz) can be achieved. 37% slices can be reduced by reducing the execution time to 192 times.
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Keyword(in English) FPGA / Custum Computer / Computational Fluid Dynamics
Paper # RECONF2009-18
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Committee RECONF
Conference Date 2009/5/7(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Acceleration of UPACS subroutines with FPGAs
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Custum Computer
Keyword(3) Computational Fluid Dynamics
1st Author's Name Takaaki YOKOYAMA
1st Author's Affiliation Faculty of science and Technology, Keio University()
2nd Author's Name Hirokazu MORISHITA
2nd Author's Affiliation Faculty of science and Technology, Keio University
3rd Author's Name Yasunori OSANA
3rd Author's Affiliation Department of Computer and Information Science, Seikei University
4th Author's Name Naoyuki FUJITA
4th Author's Affiliation ARD Japan Aerospace Exploration Agency
5th Author's Name Hideharu AMANO
5th Author's Affiliation Faculty of science and Technology, Keio University
Date 2009-05-15
Paper # RECONF2009-18
Volume (vol) vol.109
Number (no) 26
Page pp.pp.-
#Pages 6
Date of Issue