Presentation 2009-05-15
Evaluation of a High-speed Classification System using Dynamic and Partial Reconfiguration
Hiroyuki KAWAI, Yoshiki YAMAGUCHI, Moritoshi YASUNAGA,
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Abstract(in English) In this paper, we extend DDI (Direct Data Implementation), that is pattern data are directly transformed into logic circuits and they are implemented on FPGAs. Dynamic DDI is, then, proposed as improved DDI. The main features of Dynamic DDI are dynamic and partial reconfiguration is undertaken and an on-chip system can be constructed. We develop a few kinds of prototype systems applied to Dynamic DDI and evaluate their performance. From the result of experiments using the systems, the difference between Dynamic DDI and DDI is compared and effectiveness of Dynamic DDI is shown.
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Keyword(in English) FPGA / Dynamic and Partial Reconfiguration / Pattern recognition
Paper # RECONF2009-13
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Committee RECONF
Conference Date 2009/5/7(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of a High-speed Classification System using Dynamic and Partial Reconfiguration
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Dynamic and Partial Reconfiguration
Keyword(3) Pattern recognition
1st Author's Name Hiroyuki KAWAI
1st Author's Affiliation Graduate school of Systems and Information Engineering, University of Tsukuba()
2nd Author's Name Yoshiki YAMAGUCHI
2nd Author's Affiliation Graduate school of Systems and Information Engineering, University of Tsukuba
3rd Author's Name Moritoshi YASUNAGA
3rd Author's Affiliation Graduate school of Systems and Information Engineering, University of Tsukuba
Date 2009-05-15
Paper # RECONF2009-13
Volume (vol) vol.109
Number (no) 26
Page pp.pp.-
#Pages 6
Date of Issue