Presentation 2009-05-15
Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis
Yohei HORI, Mai ITOH, Hideki IMAI,
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Abstract(in English) Cryptography is widely applied to various consumer electronics to protect digital contents, users' privacy, product confidentiality and so on. However, the development period of cryptographic hardware is exceedingly longer than that of software. Behavior-level synthesis could solve this problem, nevertheless its effectiveness is vague so far. This paper reveals the feasibility of behavior-level synthesis for the development of cryptographic hardware and discusses the optimal coding scheme to achieve high-performance hardware.
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Keyword(in English) behavior-level synthesis / cryptographic hardware / FPGA / AES
Paper # RECONF2009-12
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Committee RECONF
Conference Date 2009/5/7(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis
Sub Title (in English)
Keyword(1) behavior-level synthesis
Keyword(2) cryptographic hardware
Keyword(3) FPGA
Keyword(4) AES
1st Author's Name Yohei HORI
1st Author's Affiliation Research and Development Initiative, Chuo University()
2nd Author's Name Mai ITOH
2nd Author's Affiliation Faculty of Science and Engineering, Chuo University
3rd Author's Name Hideki IMAI
3rd Author's Affiliation Faculty of Science and Engineering, Chuo University:National Institute of Advanced Industrial Science and Technology (AIST), Research Center for Information Security (RCIS)
Date 2009-05-15
Paper # RECONF2009-12
Volume (vol) vol.109
Number (no) 26
Page pp.pp.-
#Pages 6
Date of Issue