| Presentation | 2009-05-14 A Power of FPGA Redection Using FPGA Routing Structure Based on the Small-world Network Shoichi NISHIDA, Yuzo NISHIOKA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The performance of field-programmable gate arrays (FPGA) has improved dramatically owing to new process technology. But, FPGA has a lot of problem in new process technology. Particularly the issue of FPGA's power consumption is serious because FPGA has a lot of routing resources. We propose to apply the small-wrold network to the routing structure of FPGA's for the power issue. As the small-world routing structure has not a few low-load shortcut lines. The shortcut lines decrease the average number of node-to-node steps. we take advantage of these lines for the high activity paths of circuit. As a result the average power is decreased 8% as composed with a conventional routing structure. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Low Power / Routing Structure / Small-world Network |
| Paper # | RECONF2009-4 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/5/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Power of FPGA Redection Using FPGA Routing Structure Based on the Small-world Network |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Low Power |
| Keyword(3) | Routing Structure |
| Keyword(4) | Small-world Network |
| 1st Author's Name | Shoichi NISHIDA |
| 1st Author's Affiliation | Graduate School of Science and Technology, Kumamoto University() |
| 2nd Author's Name | Yuzo NISHIOKA |
| 2nd Author's Affiliation | Hitaci-Omron Terminal Solutions Corporation, Asahi Works |
| 3rd Author's Name | Motoki AMAGASAKI |
| 3rd Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 4th Author's Name | Masahiro IIDA |
| 4th Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 5th Author's Name | Toshinori SUEYOSHI |
| 5th Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| Date | 2009-05-14 |
| Paper # | RECONF2009-4 |
| Volume (vol) | vol.109 |
| Number (no) | 26 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |