| Presentation | 2009-05-14 Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs Sen IN, Hiroki MATSUTANI, Daihan WANG, Michihiro KOIBUCHI, Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The on-chip interconnection network has been used to connect many modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance and cost of the system, and various network topologies have been proposed so far. To reveal cost-efficient on-chip network structure in the reconfigurable systems, in this paper, we estimate the performance of 2-D mesh, 2-D torus, fat trees, Spidergon, and Concentrated mesh by using a network simulator. Then these topologies are synthesized by using the Xilinx ISE in order to show the number of slices required for each topology. The evaluation results show that Concentrated mesh outperforms 2D-mesh in terms of performance and cost. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network-on-Chip / k-ary n-cube / Spidergon / Fat-Tree / Concentrated Mesh / FPGA / Topology |
| Paper # | RECONF2009-3 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/5/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs |
| Sub Title (in English) | |
| Keyword(1) | Network-on-Chip |
| Keyword(2) | k-ary n-cube |
| Keyword(3) | Spidergon |
| Keyword(4) | Fat-Tree |
| Keyword(5) | Concentrated Mesh |
| Keyword(6) | FPGA |
| Keyword(7) | Topology |
| 1st Author's Name | Sen IN |
| 1st Author's Affiliation | Department of Information and Computer Science, Keio University() |
| 2nd Author's Name | Hiroki MATSUTANI |
| 2nd Author's Affiliation | Department of Information and Computer Science, Keio University |
| 3rd Author's Name | Daihan WANG |
| 3rd Author's Affiliation | Department of Information and Computer Science, Keio University |
| 4th Author's Name | Michihiro KOIBUCHI |
| 4th Author's Affiliation | National Institute of Informatics |
| 5th Author's Name | Hideharu AMANO |
| 5th Author's Affiliation | Department of Information and Computer Science, Keio University |
| Date | 2009-05-14 |
| Paper # | RECONF2009-3 |
| Volume (vol) | vol.109 |
| Number (no) | 26 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |