Presentation 2009-05-14
Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3
Yoshihiro YASUDA, Yoshiki SAITO, Toru SANO, Masaru KATO, Hideharu AMANO,
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Abstract(in English) Dynamically Reconfigurable Processor Array (DRPA) has been received an attention as a flexible and power efficient off-loading engine for embedded devices. MuCCRA, our original DRPA, has been developed to research on the methond for lowering its power consumption. In this paper, the third prototype chip MuCCRA-3 is introduced. As a result of evaluation, MuCCRA-3 has 30 times better energy efficiency than MuCCRA-1, implemented with 180nm process, and 200 times than the DSP with 130nm process.
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Keyword(in English) Dynamically Reconfigurable Processor Array / Real Chip Evaluation
Paper # RECONF2009-2
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Committee RECONF
Conference Date 2009/5/7(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor Array
Keyword(2) Real Chip Evaluation
1st Author's Name Yoshihiro YASUDA
1st Author's Affiliation Department of Information and Computer Science, Keio University()
2nd Author's Name Yoshiki SAITO
2nd Author's Affiliation Department of Information and Computer Science, Keio University
3rd Author's Name Toru SANO
3rd Author's Affiliation Department of Information and Computer Science, Keio University
4th Author's Name Masaru KATO
4th Author's Affiliation Department of Information and Computer Science, Keio University
5th Author's Name Hideharu AMANO
5th Author's Affiliation Department of Information and Computer Science, Keio University
Date 2009-05-14
Paper # RECONF2009-2
Volume (vol) vol.109
Number (no) 26
Page pp.pp.-
#Pages 6
Date of Issue