| Presentation | 2009-05-14 Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension Ken'ichi UMEDA, Takuro UCHIDA, Kazuya TANIGAWA, Tetsuo HIRONAKA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed the reconfigurable processor Hy-DiSC for stream processing. Hy-DiSC processor consists of MeP and DS-HIE processor: MeP executes serial part of program and controls DS-HIE processor, and DS-HIE processor executes stream processing part of program. In cooperation of MeP and DS-HIE processor, MeP needs to constantly supply data to DS-HIE processor to achieve high throughput. But it needs frequent memory access. If frequent cache miss is occurred on the memory access, the throughput was reduced by the increase of the latency of data supplying. Therefore it is important to consider about the efficiency of memory access for Hy-DiSC processor. This paper shows two evaluations about memory accesses: data transfer latency on different cache size, and execution cycles on different data block size. To evaluate these effects by memory access, we have developed Hy-DiSC simulator. From the results, the effect to performance caused by cache size was small, but we found that the bottleneck was the control of the DS-HIE processor executed by MeP. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable Processor / Hy-DiSC / MeP / Memory Access / Performance Evaluation |
| Paper # | RECONF2009-1 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/5/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable Processor |
| Keyword(2) | Hy-DiSC |
| Keyword(3) | MeP |
| Keyword(4) | Memory Access |
| Keyword(5) | Performance Evaluation |
| 1st Author's Name | Ken'ichi UMEDA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Takuro UCHIDA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Kazuya TANIGAWA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Tetsuo HIRONAKA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| Date | 2009-05-14 |
| Paper # | RECONF2009-1 |
| Volume (vol) | vol.109 |
| Number (no) | 26 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |