Presentation 2009-04-21
Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults
Hideo KOHINATA, Kohei MARUMOTO, Masayuki ARAI, Satoshi FUKUMOTO,
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Abstract(in English) This paper proposes a novel technique to improve the reliability of sequential circuits. The proposed technique adopts the space-time redundancy which improves the reliability to multiple transient faults. The supposed fault model for this technique is the one in which multiple flip-flop circuits receive wrong data due to noise through signal lines of combinational circuits.
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Keyword(in English) Transient fault / Sequential circuits
Paper # CPSY2009-1,DC2009-1
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Committee DC
Conference Date 2009/4/14(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults
Sub Title (in English)
Keyword(1) Transient fault
Keyword(2) Sequential circuits
1st Author's Name Hideo KOHINATA
1st Author's Affiliation Graduate School of Engneering, Tokyo Metropolitan University()
2nd Author's Name Kohei MARUMOTO
2nd Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University
3rd Author's Name Masayuki ARAI
3rd Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University
4th Author's Name Satoshi FUKUMOTO
4th Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University
Date 2009-04-21
Paper # CPSY2009-1,DC2009-1
Volume (vol) vol.109
Number (no) 12
Page pp.pp.-
#Pages 6
Date of Issue