| Presentation | 2009-05-22 Generalized Zero-offset Power Analyses for Restricted Masking Scheme Yuichi KOMANO, Hideo SHIMIZU, Hanae NOZAKI, Atsushi SHIMBO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A masking scheme is a well-known differential power analysis (DPA) countermeasure for the cryptographic module. Although the vulnerabilities of biased masks with high or low Hamming weight have been reported, a thorough discussion of the security with middle Hamming weight mask (whose weight is half of the length of processed data) seems to be lacking. Indeed, the middle Hamming weight masking scheme is tolerant of DPA and some second-order DPA. This paper proposes new power analyses to demonstrate the vulnerability of the middle Hamming weight masking scheme. Our experiments with software AES on Atmel ATMega 163 smartcard show the power of our analyses. Our analyses, motivated by the zero offset second-order DPA, are the variants of second-order DPA; however, it is unnecessary to search the combinational points of power consumption trace similar to the zero offset second-order DPA. Moreover, our analyses can also defeat the higher-order masking scheme if the Hamming weight of the resulting mask is restricted (to be half of the length of processed data etc.). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Side channel attacks / Power analysis / Zero offset 2DPA / Masking scheme / AES / Atmel ATMega 163 smartcard |
| Paper # | ISEC2009-4 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2009/5/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Generalized Zero-offset Power Analyses for Restricted Masking Scheme |
| Sub Title (in English) | |
| Keyword(1) | Side channel attacks |
| Keyword(2) | Power analysis |
| Keyword(3) | Zero offset 2DPA |
| Keyword(4) | Masking scheme |
| Keyword(5) | AES |
| Keyword(6) | Atmel ATMega 163 smartcard |
| 1st Author's Name | Yuichi KOMANO |
| 1st Author's Affiliation | Computer & Network Systems Laboratory, Corporate R&D Center, Toshiba Corporation() |
| 2nd Author's Name | Hideo SHIMIZU |
| 2nd Author's Affiliation | Computer & Network Systems Laboratory, Corporate R&D Center, Toshiba Corporation |
| 3rd Author's Name | Hanae NOZAKI |
| 3rd Author's Affiliation | Computer & Network Systems Laboratory, Corporate R&D Center, Toshiba Corporation |
| 4th Author's Name | Atsushi SHIMBO |
| 4th Author's Affiliation | Computer & Network Systems Laboratory, Corporate R&D Center, Toshiba Corporation |
| Date | 2009-05-22 |
| Paper # | ISEC2009-4 |
| Volume (vol) | vol.109 |
| Number (no) | 42 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |