| Presentation | 2009-05-20 A scan test generation method to reduce the number of detected untestable faults Hiroshi OGAWA, Masayoshi YOSHIMURA, Toshinori HOSOKAWA, Koji YAMAZAKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There are faults which can be detected by only the invalid test patterns. This is one of the causes for the overtesting. Overtesting occurs that faults on a chip are detected under invalid states using scan chains. However it is difficult to find all invalid states based on circuit structures. On the other hand, untestable faults identification can be used sequential ATPG based on time expansion models. The our proposed method is composed of generating multi cycle capture test patterns, identifying untestable faults and extracting single cycle capture patterns from multi cycle capture sequences to reduce the number of detection for untestable faults. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | untestable fault / κ cycle capture test pattern generation / scan design / time expansion model |
| Paper # | VLD2009-3 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/5/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A scan test generation method to reduce the number of detected untestable faults |
| Sub Title (in English) | |
| Keyword(1) | untestable fault |
| Keyword(2) | κ cycle capture test pattern generation |
| Keyword(3) | scan design |
| Keyword(4) | time expansion model |
| 1st Author's Name | Hiroshi OGAWA |
| 1st Author's Affiliation | Graduate School of Industrial Technology, Nihon University() |
| 2nd Author's Name | Masayoshi YOSHIMURA |
| 2nd Author's Affiliation | Graduate School of Infomation Science and Electrical Engineering, Kyushu University |
| 3rd Author's Name | Toshinori HOSOKAWA |
| 3rd Author's Affiliation | College of Industrial Technology, Nihon University |
| 4th Author's Name | Koji YAMAZAKI |
| 4th Author's Affiliation | School of Information and Communication, Meiji University |
| Date | 2009-05-20 |
| Paper # | VLD2009-3 |
| Volume (vol) | vol.109 |
| Number (no) | 34 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |