| Presentation | 2009-01-14 A Power Saving Scheme on Multicore Processors Using OSCAR API Ryo NAKAGAWA, Masayoshi MASE, Jun SHIRAKO, Keiji KIMURA, Hironori KASAHARA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Effective power reduction of an application program on multicore processors requires appropriate power control for each on-chip resource by compilers or users. These low power techniques need an application program interface (API) to realize power control in a user program. This paper proposes a power saving scheme for multicore processors using OSCAR API developed in NEDO "Multicore for Realtime Consumer Electronics" project. The proposed scheme has been implemented in OSCAR compiler to realize the power reduction for fastest execution mode, which minimizes power consumption without performance degradation, and the realtime execution mode to minimize power consumption under realtime constrains. The proposed scheme is evaluated on an 8 cores SH4A multicore processor RP2, newly developed for consumer electronics by Renesas Technology Corp., Hitachi, Ltd. and Waseda University in the above project. For the fastest execution mode, consumed energy was reduced by 13.05% for SPEC2000 art and 3.99% for SPEC2000 equake. Also, for the realtime execution mode, consumed power was reduced by 87.9% for AAC encoder and 73.2% for MPEG2 decoder. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Muticore Processor / Low Power / Parallelizing Compiler / API |
| Paper # | ICD2008-145 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2009/1/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Power Saving Scheme on Multicore Processors Using OSCAR API |
| Sub Title (in English) | |
| Keyword(1) | Muticore Processor |
| Keyword(2) | Low Power |
| Keyword(3) | Parallelizing Compiler |
| Keyword(4) | API |
| 1st Author's Name | Ryo NAKAGAWA |
| 1st Author's Affiliation | Department of Computer Science, Waseda University() |
| 2nd Author's Name | Masayoshi MASE |
| 2nd Author's Affiliation | Department of Computer Science, Waseda University |
| 3rd Author's Name | Jun SHIRAKO |
| 3rd Author's Affiliation | Department of Computer Science, Waseda University |
| 4th Author's Name | Keiji KIMURA |
| 4th Author's Affiliation | Department of Computer Science, Waseda University |
| 5th Author's Name | Hironori KASAHARA |
| 5th Author's Affiliation | Department of Computer Science, Waseda University |
| Date | 2009-01-14 |
| Paper # | ICD2008-145 |
| Volume (vol) | vol.108 |
| Number (no) | 375 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |