Presentation 2009-01-14
Fine-Grained Dynamic Sleep Control on the Combination of High-Perfomance Core and Low-Power Cores
Naomi SEKI, Lei ZHAO, Daisuke IKEBUCHI, Yu KOJIMA, Hideharu AMANO,
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Abstract(in English) A heterogeneous multi-core processor, which is consists of the combination of fine-grained power gating for split ALU and coarse-grain power gating for cores, is designed and evaluated. Although the high-perfomance core (HP-Core) and the low-power core (LP-Core) run with the same ISA, the HP-Core is a Superscaler with higher clock frequency, compared with the LP-Core. Each core shares 16KB L1 Cache and TLB, and is designed using Fujitsu 65nm CMOS technology. As a result, the perfomance of HP-Core increased by 24%. The leakage power is reduced by 46% for executing Dijkstra and Blowfish, while the power comsuption is increased by 63% for Quick Sort and JPEG. Area overhead is 9.2%.
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Paper # ICD2008-143
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Conference Date 2009/1/6(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Fine-Grained Dynamic Sleep Control on the Combination of High-Perfomance Core and Low-Power Cores
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Keyword(1)
1st Author's Name Naomi SEKI
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Lei ZHAO
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Daisuke IKEBUCHI
3rd Author's Affiliation Graduate School of Science and Technology, Keio University
4th Author's Name Yu KOJIMA
4th Author's Affiliation Graduate School of Science and Technology, Keio University
5th Author's Name Hideharu AMANO
5th Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2009-01-14
Paper # ICD2008-143
Volume (vol) vol.108
Number (no) 375
Page pp.pp.-
#Pages 6
Date of Issue