Presentation 2009-01-14
Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Teruo KAMIYAMA, Yasutaka WADA, Akihiro HAYASHI, Masayoshi MASE, Hirohumi NAKANO, Takeshi WATANABE, Keiji KIMURA, Hironori KASAHARA,
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Abstract(in English) This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose cores, an automatic parallelizing compiler that cooperatively works with the heterogeneous multicore, a heterogeneous multicore architecture simulation environment, and performance evaluation results with the simulation environment. For the performance evaluation, multimedia applications written in C or Fortran, considered with parallelization by the compiler, are used. As a result, the evaluated heterogeneous multicore having two general purpose cores and two accelerator cores achieves 9.82 times speedup from MP3 encoder. This architecture also achieves 14.64 times speedup from JPEG2000 encoder.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Heterogeneous multicore / OSCAR Compiler
Paper # ICD2008-140
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Conference Date 2009/1/6(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Sub Title (in English)
Keyword(1) Heterogeneous multicore
Keyword(2) OSCAR Compiler
1st Author's Name Teruo KAMIYAMA
1st Author's Affiliation Department of Computer Science and Engineering, Waseda University()
2nd Author's Name Yasutaka WADA
2nd Author's Affiliation Department of Computer Science and Engineering, Waseda University
3rd Author's Name Akihiro HAYASHI
3rd Author's Affiliation Department of Computer Science and Engineering, Waseda University
4th Author's Name Masayoshi MASE
4th Author's Affiliation Department of Computer Science and Engineering, Waseda University
5th Author's Name Hirohumi NAKANO
5th Author's Affiliation Department of Computer Science and Engineering, Waseda University
6th Author's Name Takeshi WATANABE
6th Author's Affiliation Department of Computer Science and Engineering, Waseda University
7th Author's Name Keiji KIMURA
7th Author's Affiliation Department of Computer Science and Engineering, Waseda University
8th Author's Name Hironori KASAHARA
8th Author's Affiliation Department of Computer Science and Engineering, Waseda University
Date 2009-01-14
Paper # ICD2008-140
Volume (vol) vol.108
Number (no) 375
Page pp.pp.-
#Pages 6
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