Presentation 2009-01-14
A Low-Power Field-Programmable VLSI Based on Autonomous Fine-Grain Power Gating
Masanori HARIYAMA, Shota ISHIHARA, Michitaka KAMEYAMA,
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Abstract(in English) This paper presents a field-programmable VLSI (FPVLSI) based on fine-grain power gating with small overheads. The asynchronous architecture inherently has the information about the activity of a cell. This greatly reduces the area and power overheads of power gating control because a sequencer and a power-control-timing storage are not required. Detecting data arrival in advance prevents delay for wake-up and unnecessary power switching. The proposed architecture is fabricated in the ASPLA 90nm CMOS process with dual threshold voltages. When the utilization is 20%, the static power is reduced to 34%.
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Keyword(in English) FPGA / Asynchronous architecture / bit-serial architecture
Paper # ICD2008-138
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Conference Date 2009/1/6(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low-Power Field-Programmable VLSI Based on Autonomous Fine-Grain Power Gating
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Asynchronous architecture
Keyword(3) bit-serial architecture
1st Author's Name Masanori HARIYAMA
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Shota ISHIHARA
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Michitaka KAMEYAMA
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2009-01-14
Paper # ICD2008-138
Volume (vol) vol.108
Number (no) 375
Page pp.pp.-
#Pages 5
Date of Issue