| Presentation | 2009-01-13 Customizable Dataplane Processors for System-on-Chip Takayuki SUGAWARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The architecture of Xtensa processor, which is the leading customizable processor for System-on-Chip (SOC), and its user examples are illustrated. The risks around the large SOC development are decreased by introducing these processor solutions. At the same time, the both of the performance requirement and the low-power requirement are achieved simultaneously by using the customizable processor platform. The automated processor generation and related software tools generation enable to execute the iterative system architecture update at design phase and increases the design productivity rate. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Customizable Processor / Dataplane Processor Unit / DPU |
| Paper # | ICD2008-134 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2009/1/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Customizable Dataplane Processors for System-on-Chip |
| Sub Title (in English) | |
| Keyword(1) | Customizable Processor |
| Keyword(2) | Dataplane Processor Unit |
| Keyword(3) | DPU |
| 1st Author's Name | Takayuki SUGAWARA |
| 1st Author's Affiliation | Tensilica K.K.() |
| Date | 2009-01-13 |
| Paper # | ICD2008-134 |
| Volume (vol) | vol.108 |
| Number (no) | 375 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |