| Presentation | 2009-01-13 Evalutions of Prediction Router for Low-Latency On-Chip Networks Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, Tsutomu YOSHINAGA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To reduce the communication latency on recent many-core architectures, we have proposed a low-latency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the communication latency is to select the prediction algorithm that offers a high hit rate for a given network environment. In this paper, the prediction routers support multiple prediction algorithms and select one of them in response to the network topology, routing algorithm, and traffic pattern. To investigate optimal prediction algorithm for a given network, the prediction router architecture is applied to four many-core architectures. For each case study, the router is designed with a 65nm CMOS process and evaluated in terms of the area, energy, prediction hit rate, and latency. This paper shows their area- and energy-overhead, and the pros and cons of each prediction algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | ICD2008-129 |
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| Committee | ICD |
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| Conference Date | 2009/1/6(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evalutions of Prediction Router for Low-Latency On-Chip Networks |
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| 1st Author's Name | Hiroki MATSUTANI |
| 1st Author's Affiliation | Graduate School of Science and Technology, Keio University() |
| 2nd Author's Name | Michihiro KOIBUCHI |
| 2nd Author's Affiliation | National Institute of Informatics |
| 3rd Author's Name | Hideharu AMANO |
| 3rd Author's Affiliation | Graduate School of Science and Technology, Keio University |
| 4th Author's Name | Tsutomu YOSHINAGA |
| 4th Author's Affiliation | Graduate School of Information Systems, The University of Electro-Communications |
| Date | 2009-01-13 |
| Paper # | ICD2008-129 |
| Volume (vol) | vol.108 |
| Number (no) | 375 |
| Page | pp.pp.- |
| #Pages | 6 |
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