Presentation 2009-01-30
An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation
Yosuke KAWANAKA, Shin'ichi WAKABAYASHI, Shinobu NAGAYAMA,
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Abstract(in English) This paper proposes an organization of special-purpose hardware dedicated to pattern matching for packet inspection in network intrusion detection systems (NIDSs). The proposed matching machine receives virus patterns as input, which are described as regular expressions defined in Snort NIDS software, and performs efficient matching. For instant updating of pattern sets, the proposed matching machine consists of an existing matching machine, in which patterns are implemented as hardware, and a new matching machine, in which patterns can be set during the execution time of matching.
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Keyword(in English) String Matching / NIDS / Regular Expression / Snort
Paper # VLD2008-123,CPSY2008-85,RECONF2008-87
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Committee VLD
Conference Date 2009/1/22(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation
Sub Title (in English)
Keyword(1) String Matching
Keyword(2) NIDS
Keyword(3) Regular Expression
Keyword(4) Snort
1st Author's Name Yosuke KAWANAKA
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Shin'ichi WAKABAYASHI
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
3rd Author's Name Shinobu NAGAYAMA
3rd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
Date 2009-01-30
Paper # VLD2008-123,CPSY2008-85,RECONF2008-87
Volume (vol) vol.108
Number (no) 412
Page pp.pp.-
#Pages 6
Date of Issue