Presentation 2009-01-30
Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA
Masaru KATO, Toru SANO, Hideharu AMANO,
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Abstract(in English) In the MuCCRA (Multi-Core Configurable Reconfigurable Architecture) project, an architecture of configurable low-power multi-core dynamically reconfigurable processor has been investigated. A dynamically processor called MuCCRA is consisting of a number of PEs, and its interconnection of PEs gives a large effect on the total area, energy and performance. In this paper, we desgin three types of interconnection; direct connection, island-style connection and hybrid connection with three differrent PE array sizes, and evaluate these area, energy and performance. As a result, a MuCCRA with hybrid interconnection which has the highest degree of flexibility is able to execute alpha-blend faster than other MuCCRAs, but requires more area by 25% and consumes higher energy by 15% than MuCCRA with direct interconnection.
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Keyword(in English) Dynamically Reconfigurable Processor / Interconnection Network
Paper # VLD2008-122,CPSY2008-84,RECONF2008-86
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Committee VLD
Conference Date 2009/1/22(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor
Keyword(2) Interconnection Network
1st Author's Name Masaru KATO
1st Author's Affiliation Faculty of Science and Technology, Keio University()
2nd Author's Name Toru SANO
2nd Author's Affiliation Faculty of Science and Technology, Keio University
3rd Author's Name Hideharu AMANO
3rd Author's Affiliation Faculty of Science and Technology, Keio University
Date 2009-01-30
Paper # VLD2008-122,CPSY2008-84,RECONF2008-86
Volume (vol) vol.108
Number (no) 412
Page pp.pp.-
#Pages 6
Date of Issue