| Presentation | 2009-01-30 Delay Evaluation of a 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation Naoto MIYAMOTO, Tadahiro OHMI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circuits, each sub-circuit is assigned to a context, and the MC-FPGA sequentially executes all the contexts one by one. So, the total execution delay is the sum of the delays of all the contexts. It is, therefore, said that the total execution delay of the MC-FPGA increases proportional to the number of contexts used. However, in this paper, we show that the total execution delay remains constant if a shift-register-type temporal communication module (SR-TCM) is used instead of D-FlipFlop (D-FF) to implement sequential circuits. The SR-TCM is used not only for sequential circuit like D-FF, but also for signal communication from preceding context to succeeding contexts. In order to quantify the execution delay, a MC-FPGA named Flexible Processor (FP), which equips the SR-TCM, have been designed and fabricated in 90nm CMOS process technology. From the measurement results, the total execution delay of the FP was kept constant regardless of the number of contexts used. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multi-Context / FPGA / Temporal Signal Communication / Temporal Circuit Partitioning |
| Paper # | VLD2008-119,CPSY2008-81,RECONF2008-83 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 2009/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Delay Evaluation of a 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation |
| Sub Title (in English) | |
| Keyword(1) | Multi-Context |
| Keyword(2) | FPGA |
| Keyword(3) | Temporal Signal Communication |
| Keyword(4) | Temporal Circuit Partitioning |
| 1st Author's Name | Naoto MIYAMOTO |
| 1st Author's Affiliation | New Industry Creation Hatchery Center, Tohoku University() |
| 2nd Author's Name | Tadahiro OHMI |
| 2nd Author's Affiliation | New Industry Creation Hatchery Center, Tohoku University |
| Date | 2009-01-30 |
| Paper # | VLD2008-119,CPSY2008-81,RECONF2008-83 |
| Volume (vol) | vol.108 |
| Number (no) | 412 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |