| Presentation | 2009-01-30 Automatic Equivalence Specification between Two Sequential Circuits in High-Level Design Jinmei XU, Tasuku NISHIHARA, Takeshi MATSUMOTO, Masahiro FUJITA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There are several verifiers available that check the equivalence of high-level designs. In those tools, the equivalence to be checked is specified with the latency and throughput of the given designs. However, specifying them is not easy since it requires the users to have the detailed knowledge of the design and the equivalence specification method. In this work, we propose a method to infer the latency and throughput of a given high-level design. In the proposed method, using the results of random simulation, possbile latencies and throughputs are provided. In addition, to reduce the number of possible latencies and throughputs, we introduce a tag-simulation method where all possible latencies in the given design are statically derived. Through the experiments on example designs, we show that the proposed method is able to show correct latencies and throughputs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-level design / equivalence checking / equivalence specification / sequential circuit |
| Paper # | VLD2008-109,CPSY2008-71,RECONF2008-73 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Automatic Equivalence Specification between Two Sequential Circuits in High-Level Design |
| Sub Title (in English) | |
| Keyword(1) | High-level design |
| Keyword(2) | equivalence checking |
| Keyword(3) | equivalence specification |
| Keyword(4) | sequential circuit |
| 1st Author's Name | Jinmei XU |
| 1st Author's Affiliation | Department of Electronics Engineering, University of Tokyo() |
| 2nd Author's Name | Tasuku NISHIHARA |
| 2nd Author's Affiliation | Department of Electronics Engineering, University of Tokyo |
| 3rd Author's Name | Takeshi MATSUMOTO |
| 3rd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 4th Author's Name | Masahiro FUJITA |
| 4th Author's Affiliation | VLSI Design and Education Center, University of Tokyo:Core Research for Evolution Science and Technology, Japan Science and Technology Agency |
| Date | 2009-01-30 |
| Paper # | VLD2008-109,CPSY2008-71,RECONF2008-73 |
| Volume (vol) | vol.108 |
| Number (no) | 412 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |