| Presentation | 2009-01-29 Leakage Power Reduction of a Dynamically Reconfigurable Processor using the dual Vth technique Keiichiro HIRAI, Toru SANO, Masaru KATO, Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Leakage power reduction techniques of dynamically reconfigurable processors by using Dual-Vth cells are proposed. Low speed Processing Elements (PEs) with high-Vth cells whose leakage power is low and High speed PEs with low-Vth cells whose leakage power is high are mixed in the same array. The maximum clock frequency of dynamically reconfigurable processor arrays is decided only with the critical path when the data flow graph of the target application is mapped. Thus, if the critical path can be mapped only on the low-Vth PEs, the leakage power can be reduced without degrading performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable Processor / Low Power Design / Dual-Vth |
| Paper # | VLD2008-93,CPSY2008-55,RECONF2008-57 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Leakage Power Reduction of a Dynamically Reconfigurable Processor using the dual Vth technique |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor |
| Keyword(2) | Low Power Design |
| Keyword(3) | Dual-Vth |
| 1st Author's Name | Keiichiro HIRAI |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Toru SANO |
| 2nd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 3rd Author's Name | Masaru KATO |
| 3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 4th Author's Name | Hideharu AMANO |
| 4th Author's Affiliation | Faculty of Science and Technology, Keio University |
| Date | 2009-01-29 |
| Paper # | VLD2008-93,CPSY2008-55,RECONF2008-57 |
| Volume (vol) | vol.108 |
| Number (no) | 412 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |