Presentation 2009-02-16
A Secure Scan Design Approach Using Extended de Bruijn Graph
Hideo FUJIWARA, Marie Engelene J. OBIEN,
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Abstract(in English) Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. This paper introduces a new secure scan design approach using extended de Bruijn graph, which aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan chains to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. Moreover, no additional keys and controller circuits outside of the scan chain are needed, thus making the scheme low-cost and efficient.
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Keyword(in English) Secure scan design / Security / Testability / Design-for-test / Extended de Bruijn graph
Paper # DC2008-78
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Committee DC
Conference Date 2009/2/9(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Secure Scan Design Approach Using Extended de Bruijn Graph
Sub Title (in English)
Keyword(1) Secure scan design
Keyword(2) Security
Keyword(3) Testability
Keyword(4) Design-for-test
Keyword(5) Extended de Bruijn graph
1st Author's Name Hideo FUJIWARA
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology()
2nd Author's Name Marie Engelene J. OBIEN
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
Date 2009-02-16
Paper # DC2008-78
Volume (vol) vol.108
Number (no) 431
Page pp.pp.-
#Pages 6
Date of Issue