| Presentation | 2009-02-16 Resource Binding to Minimize the Number of RTL Paths Yuichi UEMOTO, Satoshi OHTAKE, Michiko INOUE, Hideo FUJIWARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Though path delay testing is promising to detect small delay in a VLSI circuit, it has a practical problem that the number of paths in a circuit is enormous. In this paper, in order to reduce path delay testing cost, we propose a resource biding method to minimize the number of paths and the number of true paths during high level synthesis, where true paths are paths whose path delay faults should be tested. The proposed method considers resource sharing among RTL paths (i.e., paths between registers in RTL circuit), and hence, synthesizes RTL circuits with small number of paths. Experimental results show the effectiveness of the proposed method, and also show that small number of paths induces small area of RTL circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high level synthesis / path delay fault / resource binding / false path identification |
| Paper # | DC2008-77 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2009/2/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Resource Binding to Minimize the Number of RTL Paths |
| Sub Title (in English) | |
| Keyword(1) | high level synthesis |
| Keyword(2) | path delay fault |
| Keyword(3) | resource binding |
| Keyword(4) | false path identification |
| 1st Author's Name | Yuichi UEMOTO |
| 1st Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology |
| 3rd Author's Name | Michiko INOUE |
| 3rd Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology |
| 4th Author's Name | Hideo FUJIWARA |
| 4th Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology |
| Date | 2009-02-16 |
| Paper # | DC2008-77 |
| Volume (vol) | vol.108 |
| Number (no) | 431 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |