Presentation | 2009-02-16 Note on Small Delay Fault Model for Intra-Gate Resistive Open Defects Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We discuss the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the transition delay fault model is insufficient to detect weak opens inside the gate. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | small delay fault / resistive open defect / intra-gate open / transition delay fault |
Paper # | DC2008-75 |
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Committee | DC |
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Conference Date | 2009/2/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Note on Small Delay Fault Model for Intra-Gate Resistive Open Defects |
Sub Title (in English) | |
Keyword(1) | small delay fault |
Keyword(2) | resistive open defect |
Keyword(3) | intra-gate open |
Keyword(4) | transition delay fault |
1st Author's Name | Masayuki Arai |
1st Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University() |
2nd Author's Name | Akifumi Suto |
2nd Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
3rd Author's Name | Kazuhiko Iwasaki |
3rd Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
4th Author's Name | Katsuyuki Nakano |
4th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
5th Author's Name | Michihiro Shintani |
5th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
6th Author's Name | Kazumi Hatayama |
6th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
7th Author's Name | Takashi Aikyo |
7th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
Date | 2009-02-16 |
Paper # | DC2008-75 |
Volume (vol) | vol.108 |
Number (no) | 431 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |