Presentation 2009-02-16
Decimal adder using abacus architecture and its application to residue arithmetic
Tadahito IIJIMA, Shugang WEI,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In a decimal number system, arithmetic circuits are implemented by using the binary number representations well known as BCD codes, so that binary arithmetic circuits can be used for the realization of a decimal arithmetic circuit. However, the carry propagation will limit the speed of operations such as addition, subtraction and multiplication. In this paper, the abacus architecture is introduced to achieve high speed arithmetic circuits for the decimal number system. First we give a fast calculation method to obtain the carries in additions in the abacus architecture. Then we present residue addition algorithm using the abacus addition. The design and simulation results show that the proposed decimal arithmetic circuits based on the abacus architecture are high speed compared to the binary methods and our previous works.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) abacus / decimal additon / residue number system / VHDL / synopsys
Paper # DC2008-71
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Committee DC
Conference Date 2009/2/9(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Decimal adder using abacus architecture and its application to residue arithmetic
Sub Title (in English)
Keyword(1) abacus
Keyword(2) decimal additon
Keyword(3) residue number system
Keyword(4) VHDL
Keyword(5) synopsys
1st Author's Name Tadahito IIJIMA
1st Author's Affiliation Gunma Univ.()
2nd Author's Name Shugang WEI
2nd Author's Affiliation Gunma Univ.
Date 2009-02-16
Paper # DC2008-71
Volume (vol) vol.108
Number (no) 431
Page pp.pp.-
#Pages 5
Date of Issue